The invention relates to a differential encoder and decoder system for transmitting or storing input signals, comprising a differential pulse code modulator at the input end and receiving the input signals applied to a system input in the form of a sequence of signal samples successively occurring at a first clock rate and supplying a quantized error signal sample from the modulator output at a second clock rate, and comprising a differential pulse code demodulator at the output end, receiving at a demodulator input the quantized error signal samples in the form of a sequence occurring at said second clock rate and generating a reconstructed signal sample for each error signal sample and applying it to a system output.
Such systems are generally known and are used to represent the input signals with a minimum possible amount number of bits without distorting the reconstructed signals to a too large extent. A differential pulse code modulator for such a system is known, for example from the magazine "IEEE Transactions on Communications", Volume Com-30, No. 5, May 1982, pages 1174-1184 and has the principle structure shown in FIG. 1. The input signal samples s(n) are successively applied to the input 1 at a clock rate 1/t, in which n is an arbitrary point of time within the sequence. In the differential stage 2, an internally generated prediction signal sample s"(n) is subtracted from each input signal sample s(n), which sample is applied via the lead 9, and the error signal sample e(n) is produced at the output 3 of the differential stage 2. This error signal sample e(n) is applied to a quantizer 4 for quantizing and coding e and which supplies these quantized and coded samples to the output 5. The quantized error signal sample e'(n) is applied to the first input of a first adder 6 whose second input receives the prediction signal sample s"(n) via the lead 9 and which supplies the reconstructed signal sample s'(n) from its output lead 7 and applies it to a predictor 8. This predictor 8 successively generates the sum of a number of preceding differently weighted reconstructed signal samples s'(n-m) with the aid of multipliers and delay devices and each sum thus formed represents a prediction signal sample s"(n) which is supplied from the lead 9. Dependent on the extent of correlation among the input signal samples s(n), the range of values of the error signal sample e is considerably reduced and due to the quantization and coding, a further reduction of the information quantity is achieved so that in the case of a binary representation of all signals, the quantized error signal samples e' on the output lead 5 comprise considerably fewer bits than the input signal samples s at the input 1. Since the adder 6 uses the quantized error signal sample e' to form the reconstructed signal s', the quantization errors are constantly taken into account so that no quantization errors can be accumulated in the quantized error signal e'.
As is shown in FIG. 1, the subtraction in the differential stage 2, the formation of the quantized error signal samples e' in the quantizer 4, the addition in the adder 6 and, particularly, the formation of the weighted sum in the predictor 8 must be performed in a time-critical loop within one sampling period in order that the associated prediction signal sample s"(n+1) is available after applying an input signal samples(n) at the instant at which the next input signal sample s(n+1) arrives. These elements thus constitute the time-critical loop. At high sampling frequencies of the input signal samples, as for example in television picture signals, only a very short time is available for this sequence of processing steps within the time-critical loop so that high-speed components, which are costly and require much energy, must be used to perform the individual signal processing steps.
FIG. 3 of the above-mentioned document illustrates a conversion of the differential pulse code modulator using two predictors. However, this conversion only serves to inspect the stability of such an arrangement and does not otherwise produce the number of processing steps required within a sampling time interval.
DE-OS 34 17 139 describes a differential pulse code modulator for high processing speeds, using one adder less in the time-critical loop as compared with the state of the art. However, this adder should only be economized during summation of the prediction signal in the parallel predictors so that the time-critical loop still comprises the four elements of differential stage, quantizer, adder and predictor. EP Patent Application 176 821 describes a differential pulse code modulator in which the number of processing steps in the time-critical loop should also be reduced. For this purpose the differential stage is divided into two individual differential stages which are separated by a register. The differential stage connected immediately before the quantizer receives at its subtracting input the error signal samples multiplied by a coefficient instead of the reconstructed signal so that the time-critical loop comprises one adder less. This is, however, apparently based on the supposition that each prediction signal sample is only formed from the last preceding error signal sample by multiplying it by a coefficient which can be represented as an integral negative power of two. The extension of this arrangement to other cases, particularly to the formation of each prediction sample from a plurality of preceding error signal samples and reconstructed signal samples, cannot be concluded from this Application.